A nonvolatile semiconductor memory device has been proposed that has a stacked gate structure, in which a floating gate and a control gate are stacked. For example, a nonvolatile semiconductor memory device disclosed in JP-A-S56-129374 employs a hot hole (HH) injection mechanism to erase data. In the hot hole (HH) injection mechanism, data stored in the memory device is erased by injecting a hot hole into a floating gate. The hot hole is generated by avalanche breakdown between a drain and a semiconductor substrate.
The present inventors have investigated a relationship between the number of erase and program cycles and a change in a threshold voltage of a conventional stacked gate nonvolatile semiconductor memory device. The memory device is programmed by injecting a hot electron, which flows from a source and a drain, into a floating gate near a drain and erased by injecting a hot hole, which is generated due to avalanche breakdown between the drain and a semiconductor substrate, into the floating gate. The investigation has been conducted using five threshold data obtained per each erase and program cycle at a temperature of 25 degrees Celsius (° C.). The result of the investigation shows that the decrease in a programmed threshold voltage increases with an increase in the number of erase and program cycles. Therefore, erase and program cycle endurance of such a stacked gate nonvolatile semiconductor memory device may be low.